1. Field Of The Invention
The present invention relates to the field of electrically programmable and electrically erasable MOS devices.
2. Prior Art
Numerous read-only memories employing floating gate memory cells are well-known and commercially available. Typically, these memories are fabricated with MOS technology. Each cell includes a polycrystalline silicon (polysilicon) floating gate which is completely surrounded by electrical insulation such as silicon dioxide. Various mechanisms are used to transport charge onto the floating gate and to remove the charge from this gate. In one class of memories (EPROMs), charge is transported to the floating gate through channel hot electron injection or avalanche injection and is removed by exposing the memory to ultraviolet radiation. Another class of memories, EEPROMs, may be electrically erased as well. EEPROMs utilize a thin oxide between the floating gate and the substrate through which charge is tunneled onto and from the floating gate. In both types of devices, a second polysilicon control gate is generally employed. The control gate is electrically coupled to a supply potential and is generally used during reading and writing operations.
It is desirable to implement memory cells such as those described above on logic manufacturing technologies, so that logic functions and memory elements can be incorporated on a single chip, to form electrically programmable logic devices (EPLDs). Use of EPROM-like cells on logic technologies enhances the performance of the logic devices by allowing them to be custom configured by the user. One problem with the above-described EPROM and EEPROM technologies is that two layers of polysilicon are usually required, one for the floating gate and one for the control gate. However, double polysilicon processing is not otherwise required to manufacture MOS or CMOS logic circuits. Therefore, implementing a double poly-EPROM on current logic manufacturing technologies greatly increases processing complexity, thereby increasing costs and reducing yields.
Recently, a single polysilicon layer EPROM has been proposed (see "A Single Poly-EPROM for Custom CMOS Logic Applications" by R. Kazerounian and B. Eitan, IEEE/CICC 1986). In that paper, a memory cell utilizing a single polysilicon floating gate is described. The cell includes a floating gate n-channel transistor and a control gate. The "control gate" is an n-well which is capacitively coupled to the floating gate. The single poly-EPROM is programmed by channel hot electron injection into the floating gate and erased by exposure to UV light.
While the above memory element is compatible with single polysilicon CMOS technology, it is further desirable to produce a CMOS compatible memory cell which is electrically erasable as well as electrically programmable. It is further desirable that the memory cells should be capable of preventing "over-erase" mechanisms which occur in "flash" type devices. Finally, the memory cell should be capable of preventing "program disturb" and "D.C. erase" problems which occur in flash type devices.